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publication# 16491 rev: e amendment/ 0 issue date: november 1998 pal devices palce20v8 family ee cmos 24-pin universal programmable array logic distinctive characteristics u pin and function compatible with all pal ? 20v8 devices u electrically erasable cmos technology provides recon?gurable logic and full testability u high-speed cmos technology 5-ns propagation delay for -5 version 7.5-ns propagation delay for -7 version u direct plug-in replacement for a wide range of 24-pin pal devices u programmable enable/disable control u outputs individually programmable as registered or combinatorial u peripheral component interconnect (pci) compliant u preloadable output registers for testability u automatic register reset on power-up u cost-effective 24-pin plastic skinny dip and 28-pin plcc packages u extensive third-party software and programmer support u fully tested for 100% programming and functional yields and high reliability u programmable output polarity u 5-ns version utilizes a split leadframe for improved performance general description the palce20v8 is an advanced pal device built with low-power, high-speed, electrically- erasable cmos technology. its macrocells pr ovide a universal device ar chitecture. the palce20v8 is fully compatible with the gal20v8 and can dir ectly r eplace p al20r8 series devices and most 24-pin combinatorial pal devices. device logic is automatically contgured according to the user?s design specitcation. a design is implemented using any of a number of popular design software packages, allowing automatic creation of a programming tle based on boolean or state equations. design software also verites the design and can pr ovide test vectors for the tnished device. pr ogramming can be accomplished on standard pal device pr ogrammers. the palce20v8 utilizes the familiar sum-of-pr oducts (and/or) ar chitecture that allows users to implement complex logic functions easily and eftciently. multiple levels of combinatorial logic can always be r educed to sum-of-products form, taking advantage of the very wide input gates available in pal devices. the equations are programmed into the device thr ough ?oating-gate cells in the and logic array that can be erased electrically. com'l: h-5/7/10/15/25, q-10/15/25 ind: h-15/25, q-20/25
304 palce20v8 family the t xed or array allows up to eight data product terms per output for logic functions. the sum of these products feeds the output macrocell. each macr ocell can be programmed as registered or combinatorial with an active-high or active-low output. the output contguration is determined by two global bits and one local bit controlling four multiplexers in each macrocell. block diagram functional description the palce20v8 is a universal pal device. it has eight independently contgurable macrocells (mc 0 -mc 7 ). each macr ocell can be contgured as a registered output, combinatorial output, combinatorial i/o, or dedicated input. the programming matrix implements a pr ogrammable and logic array, which drives a txed or logic array. buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. pins 1 and 13 serve either as array inputs or as clock (clk) and output enable (oe ) for all ?ip-?ops. unused input pins should be tied dir ectly to v cc or gnd. pr oduct terms with all bits unprogrammed (disconnected) assume the logical high state, and product terms with both true and complement of any input signal connected assume a logical low state. the programmable functions on the p alce20v8 are automatically contgured from the user?s design specitcation, which can be in a number of formats. the design specitcation is proce ssed programmable and array 40 x 64 mc 0 macro mc 1 macro mc 2 macro mc 3 macro mc 4 macro mc 5 macro mc 6 macro mc 7 oe /i 11 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 10 i 1 C i 10 clk / i 0 16491e input mux. i 13 macro input mux. i 12
palce20v8 family 305 pal devices by development software to verify the design and create a programming t le. this t le, once downloaded to a programmer, contgures the device according to the user?s desired function. the user is given two design options with the p alce20v8. first, it can be pr ogrammed as an emulated pal device. this includes the pal20r8 series and most 24-pin combinatorial pal devices. the pal device programmer manufacturer will supply device codes for the standard pal architectures to be used with the p alce20v8. the pr ogrammer will program the p alce20v8 to the corr esponding pal device architecture. this allows the user to use existing standard pal device jedec t les without making any changes to them. alternatively, the device can be programmed directly as a p alce20v8. here the user must use the p alce20v8 device code. this option provides full utilization of the macrocells, allowing non-standard ar chitectures to be built. 1 1 0 x 1 0 *sg1 sg1 sl0 x dq q 1 0 1 1 0 x 1 1 1 0 0 0 0 1 v cc clk sl0 x oe to adjacent macrocell from adjacent pin 1 1 0 x 1 0 sl1 x i/o x 16491e *in macrocells mc 0 and mc 7 , sg1 is replaced by sg0 on the feedback multiplexer. figure 1. palce20v8 macrocell
306 palce20v8 family configuration options each macr ocell can be contgured as one of the following: registered output, combinatorial output, combinatorial i/o or dedicated input. in the registered output contguration, the output buffer is enabled by the oe pin. in the combinatorial contguration, the buffer is either contr olled by a product term or always enabled. in the dedicated input contguration, the buf fer is always disabled. a macrocell contgured as a dedicated input derives the input signal from an adjacent i/o. the macrocell contgurations are controlled by the cont guration control word. it contains 2 global bits (sg0 and sg1) and 16 local bits (sl0 0 through sl0 7 and sl1 0 through sl1 7 ). sg0 determines whether registers will be allowed. sg1 determines whether the p alce20v8 will emulate a p al20r8 family or a combinatorial device. within each macr ocell, sl0 x , in conjunction with sg1, selects the contguration of the macrocell and sl1 x sets the output as either active low or active high. the contguration bits work by acting as control inputs for the multiplexers in the macrocell. there are four multiplexers: a product term input, an enable select, an output select, and a feedback select multiplexer. sg1 and sl0 x are the control signals for all four multiplexers. in mc 0 and mc 7 , sg0 replaces sg1 on the feedback multiplexer. these contgurations are summarized in table 1 and illustrated in figure 2. if the p alce20v8 is contgured as a combinatorial device, the clk and oe pins may be available as inputs to the array. if the device is contgured with r egisters, the clk and oe pins cannot be used as data inputs. registered output con?guration the control bit settings are sg0 = 0, sg1 = 1 and sl0 x = 0. there is only one r egistered contguration. all eight product terms are available as inputs to the or gate. data polarity is determined by sl1 x . sl1 x is an input to the exclusive-or gate which is the d input to the ?ip- ?op. sl1 x is programmed as 1 for inverted output or 0 for non-inverted output. the ? ip-?op is loaded on the low -to-high transition of clk. the feedback path is from q on the register. the output buf fer is enabled by oe . combinatorial con?gurations the p alce20v8 has three combinatorial output contgurations: dedicated output in a non- registered device, i/o in a non-registered device and i/o in a registered device. dedicated output in a non-registered device the control settings are sg0 = 1, sg1 = 0, and sl0 x = 0. all eight product terms are available to the or gate. although the macrocell is a dedicated output, the feedback is used, with the exception of pins 18(21) and 19(23). pins 18(21) and 19(23) do not use feedback in this mode. note: 1. the pin number without parentheses refers to the skinny dip package. the pin number in parentheses refers to the plcc package.
palce20v8 family 307 pal devices dedicated input in a non-registered device the control bit settings are sg0 = 1, sg1 = 0 and sl0 x = 1. the output buffer is disabled. the feedback signal is an adjacent i/o pin. combinatorial i/o in a non-registered device the control settings are sg0 = 1, sg1 = 1, and sl0 x = 1. only seven product terms are available to the or gate. the eighth product term is used to enable the output buffer. the signal at the i/o pin is fed back to the and array via the feedback multiplexer. this allows the pin to be used as an input. combinatorial i/o in a registered device the control bit settings are sg0=0,sg1=1 and sl0 x =1. only seven product terms are available to the or gate. the eighth product term is used as the output enable. the feedback signal is the corr esponding i/o signal. table 1. macrocell con?guration sg0 sg1 sl0 x cell con?guration devices emulated sg0 sg1 sl0 x cell con?guration devices emulated device uses registers device uses no registers 0 1 0 registered output pal20r8, 20r6, 20r4 100 combinatorial output pal20l2, 18l4, 16l6, 14l8 011 combinatorial i/o pal20r6, 20r4 1 0 1 input pal20l2, 18l4, 16l6 111 combinatorial i/o pal20l8
308 palce20v8 family d q q oe clk a. registered active low d q q oe clk b. registered active high c. combinatorial i/o active low d. combinatorial i/o active high e. combinatorial output active low v cc f. combinatorial output active high v cc adjacent i/o pin g. dedicated input notes: 1. feedback is not available on pins 18 (21) and 19 (23) in the combinatorial output mode. 2. this macrocell con?guration is not available on pins 18 (21) and 19 (23). note 1 note 1 note 2 16491e figure 2. macrocell con?gurations
palce20v8 family 309 pal devices power-up reset all ?ip-? ops power up to a logic low for predictable system initialization. outputs of the palce20v8 depend on whether they are selected as r egistered or combinatorial. if registered is selected, the output will be high. if combinatorial is selected, the output will be a function of the logic. register preload the register on the p alce20v8 can be pr eloaded from the output pins to facilitate functional testing of complex state machine designs. this feature allows dir ect loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. in addition, transitions from illegal states can be verited by loading illegal states and observing proper recovery. security bit a security bit is provided on the p alce20v8 as a deterr ent to unauthorized copying of the array contguration patterns. once programmed, this bit defeats r eadback and verit cation of the programmed pattern by a device programmer, securing pr oprietary designs from competitors. the bit can only be erased in conjunction with the array during an erase cycle. electronic signature word an electronic signature word is provided in the p alce20v8. it consists of 64 bits of programmable memory that can contain any user-detned data. the signature data is always available to the user independent of the security bit. programming and erasing the p alce20v8 can be pr ogrammed on standard logic programmers. it also may be erased to reset a previously contgured device back to its unpr ogrammed state. erasure is automatically performed by the programming hardware. no special erase operation is required. quality and testability the p alce20v8 of fers a very high level of built-in quality. the erasability of the device provides a direct means of verifying performance of all ac and dc parameters. in addition, this verites complete programmability and functionality of the device to provide the highest programming and post-programming functional yields in the industry. technology the high-speed p alce20v8h is fabricated with v antis? advanced electrically erasable (ee) cmos process. the array connections are formed with pr oven ee cells. inputs and outputs are designed to be compatible with ttl devices. this technology provides str ong input clamp diodes, output slew-rate control, and a grounded substrate for clean switching. pci compliance palce20v8h devices in the -5/-7/-10 speed grades are fully compliant with the pci local bus speci?cation published by the pci special inter est gr oup. the p alce20v8h?s pr edictable timing ensures compliance with the pci ac specitcations independent of the design. on the other hand, in cpld and fpga architectures without predictable timing, pci compliance is dependent upon routing and pr oduct term distribution.
310 palce20v8 family logic diagram 0 3 4 7 8 1112 1516 19 20 2324 2728 3132 3536 39 0 7 8 15 16 23 24 31 03478111215161920 2427283132353639 i 5 i 4 i 3 i 2 i 1 clk/i 0 (2) (3) (4) (5) (6) (7) 23 1 2 3 4 5 6 clk oe i 13 23 (27) 1 1 0 x 1 0 1 0 sg0 i/o 7 22 (26) sg0 sg1 sl0 7 1 1 0 x 1 0 dq q 1 0 1 1 0 x 1 1 1 0 0 0 0 1 v cc i/o 6 21 (25) i/o 5 20 (24) 1 1 0 x 1 0 sg1 sg1 sl0 5 1 1 0 x 1 0 dq q 1 0 1 1 1 1 1 0 0 0 0 1 v cc sl0 5 0 x 1 1 0 x 1 0 i/o 4 19 (23) sg1 sg1 sl0 4 1 1 0 x 1 0 dq q 1 0 1 1 1 1 1 0 0 0 0 1 v cc sl0 4 0 x 1 1 0 x 1 0 sg1 sg1 sl0 6 1 1 0 x 1 0 dq q 1 0 1 1 1 1 1 0 0 0 0 1 v cc sl0 6 0 x v cc 24 (28) sl0 7 16491e
palce20v8 family 311 pal devices logic diagram (continued) oe/i 10 0 3 4 7 8 111215161920 23242728 3132 353639 32 39 40 47 48 55 0 3 4 7 8 1112 1516 1920 2324 2728 3132 3536 39 sg0 0 1 11 i 12 i 9 i 8 i 7 i 6 (9) (10) (11) (12) (13) (16) (17) 56 63 clk oe 1 1 0 x 1 0 i/o 3 18 (21) sg1 sl0 3 1 1 0 x 1 0 dq q 1 0 1 1 0 x 1 1 1 0 0 0 0 1 sg0 v cc i/o 2 17 (20) i/o 1 16 (19) 1 1 0 x 1 0 sg1 sg1 sl0 1 1 1 0 x 1 0 dq q 1 0 1 1 1 1 1 0 0 0 0 1 v cc sl0 1 0 x 1 1 0 x 1 0 i/o 0 15 (18) sg1 sl0 0 1 1 0 x 1 0 dq q 1 0 1 1 1 1 1 0 0 0 0 1 v cc 0 x 1 1 0 x 1 0 sg1 sg1 sl0 2 1 1 0 x 1 0 dq q 1 0 1 1 1 1 1 0 0 0 0 1 v cc sl0 2 0 x 7 8 9 10 11 sg1 sl0 3 14 13 sl0 0 16491e-4 (concluded)
312 palce20v8h-5/7/10 (coml) absolute maximum ratings storage t emperature . . . . . . . . . . . . . .-65 c to +150 c ambient t emperature with power applied . . . . . . . . . . . . . .-55 c to +125 c supply voltage with respect to gr ound . . . . . . . . . . -0.5 v to +7.0 v dc input v oltage . . . . . . . . . . . -0.5 v to v cc + 0.5 v dc output or i/o pin v oltage . . . . . . . . . . . . . . . . . -0.5 v to v cc + 0.5 v static discharge v oltage . . . . . . . . . . . . . . . . . 2001 v latchup current (t a = 0 c to 75 c) . . . . . . . . . 100 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. programming conditions may differ. operating ranges commercial (c) devices ambient t emperature (t a ) operating in free air . . . . . . . . . . . . . . . . . . . . . . . 0 c to +75 c supply voltage (v cc ) with respect to gr ound . . . . . . . . . +4.75 v to +5.25 v operating ranges de?ne those limits between which the functionality of the device is guaranteed. dc characteristics over commercial operating ranges notes: 1. these are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. parameter symbol parameter description test description min max unit v oh output high voltage i oh = -3.2 ma, v in = v ih or v il , v cc = min 2.4 v v ol output low voltage i ol = 24 ma, v in = v ih or v il , v cc = min 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs (note 1) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (note 1) 0.8 v i ih input high leakage current v in = 5.25 v, v cc = max (note 2) 10 a i il input low leakage current v in = 0 v, v cc = max (note 2) C100 a i ozh off-state output leakage current high v out = 5.25 v, v cc = max v in = v ih or v il (note 2) 10 a i ozl off-state output leakage current low v out = 0 v, v cc = max v in = v ih or v il (note 2) C100 a i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C150 ma i cc (static) supply current for -5 outputs open (i out = 0 ma), v in = 0 v v cc = max 125 ma i cc (dynamic) supply current for -7 and -10 outputs open (i out = 0 ma), v cc = max, f = 25 mhz 115 ma
palce20v8h-5/7/10 (coml) 313 pal devices capacitance 1 note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modi?ed whe re capacitance may be affected. switching characteristics over commercial operating ranges 1 notes: 1. see switching test circuit for test conditions. 2. output delay minimums for t pd , t co , t pzx , t pxz , t ea , and t er are de?ned under best case conditions. future process improvements may alter these values; therefore, minimum values are recommended for simulation purposes only. 3. skew testing takes into account pattern and switching direction differences between outputs that have equal loading. 4. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modi?ed wh ere frequency may be affected. 5. t cf is a calculated value and is not guaranteed. t cf can be found using the following equation: t cf = 1/f max (internal feedback) C t s . parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c, f = 1 mhz 5pf c out output capacitance v out = 2.0 v 8 pf parameter symbol parameter description -5 -7 -10 unit min 2 max min 2 max min 2 max t pd input or feedback to combinatorial output 1 5 3 7.5 3 10 ns t s setup time from input or feedback to clock 3 5 7.5 ns t h hold time 0 0 0 ns t co clock to output 141537.5ns t skewr skew between registered outputs (note 3) 1 1 1 ns t wl clock width low 3 4 6 ns t wh high 3 4 6 ns f max maximum frequency (note 4) external feedback 1/(t s +t co ) 142.8 100 66.7 mhz internal feedback (f cnt ) 1/(t s +t cf ) (note 5) 166 125 71.4 mhz no feedback 1/(t wh +t wl ) 166 125 83.3 mhz t pzx oe to output enable 1616210ns t pxz oe to output disable 1516210ns t ea input to output enable using product term control 2639310ns t er input to output disable using product term control 2539310ns
314 palce20v8q-10 (coml) absolute maximum ratings storage t emperature . . . . . . . . . . . . . .-65 c to +150 c ambient t emperature with power applied . . . . . . . . . . . . . .-55 c to +125 c supply voltage with respect to gr ound . . . . . . . . . . -0.5 v to +7.0 v dc input v oltage . . . . . . . . . . . -0.5 v to v cc + 0.5 v dc output or i/o pin v oltage . . . . . . . . . . . . . . . . . -0.5 v to v cc + 0.5 v static discharge v oltage . . . . . . . . . . . . . . . . . 2001 v latchup current (t a = 0 c to 75 c) . . . . . . . . . 100 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. programming conditions may differ. operating ranges commercial (c) devices ambient t emperature (t a ) operating in free air . . . . . . . . . . . . . . . 0 c to +75 c supply voltage (v cc ) with respect to gr ound . . . . . . . . . +4.75 v to +5.25 v operating ranges de?ne those limits between which the functionality of the device is guaranteed. dc characteristics over commercial operating ranges notes: 1. these are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 4. this parameter is guaranteed worst case under test conditions. refer to the i cc vs. frequency graph for typical measurements. parameter symbol parameter description test description min max unit v oh output high voltage i oh = -3.2 ma, v in = v ih or v il , v cc = min 2.4 v v ol output low voltage i ol = 24 ma, v in = v ih or v il , v cc = min 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs (note 1) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (note 1) 0.8 v i ih input high leakage current v in = 5.25 v, v cc = max (note 2) 10 a i il input low leakage current v in = 0 v, v cc = max (note 2) C100 a i ozh off-state output leakage current high v out = 5.25 v, v cc = max v in = v ih or v il (note 2) 10 a i ozl off-state output leakage current low v out = 0 v, v cc = max v in = v ih or v il (note 2) C100 a i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C150 ma i cc (dynamic) supply current for -10 outputs open (i out = 0 ma), v cc = max, f = 15 mhz (note 4) 55 ma
palce20v8q-10 (coml) 315 pal devices capacitance 1 note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modi?ed whe re capacitance may be affected. switching characteristics over commercial operating ranges 1 notes: 1. see switching test circuit for test conditions. 2. output delay minimums for t pd , t co , t pzx , t pxz , t ea , and t er are de?ned under best case conditions. future process improvements may alter these values; therefore, minimum values are recommended for simulation purposes only. 3. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modi?ed wh ere frequency may be affected. 4. t cf is a calculated value and is not guaranteed. t cf can be found using the following equation: t cf = 1/f max (internal feedback) C t s . parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c, f = 1 mhz 5pf c out output capacitance v out = 2.0 v 8 pf parameter symbol parameter description -10 unit min 2 max t pd input or feedback to combinatorial output 310ns t s setup time from input or feedback to clock 7.5 ns t h hold time 0ns t co clock to output 3 7.5 ns t wl clock width low 6ns t wh high 6ns f max maximum frequency (note 3) external feedback 1/(t s +t co ) 66.7 mhz internal feedback (f cnt ) 1/(t s +t cf ) (note 4) 71.4 mhz no feedback 1/(t wh +t wl ) 83.3 mhz t pzx oe to output enable 210ns t pxz oe to output disable 210ns t ea input to output enable using product term control 310ns t er input to output disable using product term control 310ns
316 palce20v8h-15/25 q-15/25 (coml) absolute maximum ratings storage t emperature . . . . . . . . . . . . . .-65 c to +150 c ambient t emperature with power applied . . . . . . . . . . . . . .-55 c to +125 c supply voltage with respect to gr ound . . . . . . . . . . -0.5 v to +7.0 v dc input v oltage . . . . . . . . . . . -0.5 v to v cc + 0.5 v dc output or i/o pin v oltage . . . . . . . . . . . . . . . . . -0.5 v to v cc + 0.5 v static discharge v oltage . . . . . . . . . . . . . . . . . 2001 v latchup current (t a = 0 c to 75 c) . . . . . . . . . 100 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. programming conditions may differ. operating ranges commercial (c) devices ambient t emperature (t a ) operating in free air . . . . . . . . . . . . . . . . . . . . . . . 0 c to +75 c supply voltage (v cc ) with respect to gr ound . . . . . . . . . +4.75 v to +5.25 v operating ranges de?ne those limits between which the functionality of the device is guaranteed. dc characteristics over commercial operating ranges notes: 1. these are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. parameter symbol parameter description test description min max unit v oh output high voltage i oh = -3.2 ma, v in = v ih or v il , v cc = min 2.4 v v ol output low voltage i ol = 24 ma, v in = v ih or v il , v cc = min 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs (note 1) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (note 1) 0.8 v i ih input high leakage current v in = 5.25 v, v cc = max (note 2) 10 a i il input low leakage current v in = 0 v, v cc = max (note 2) C100 a i ozh off-state output leakage current high v out = 5.25 v, v cc = max v in = v ih or v il (note 2) 10 a i ozl off-state output leakage current low v out = 0 v, v cc = max v in = v ih or v il (note 2) C100 a i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C150 ma i cc supply current outputs open (i out = 0 ma), v cc = max, f = 15 mhz h90 ma q55
palce20v8h-15/25 q-15/25 (coml) 317 pal devices capacitance 1 note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modi?ed whe re capacitance may be affected. switching characteristics over commercial operating ranges 1 notes: 1. see switching test circuit for test conditions. 2. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modi?ed wh ere frequency may be affected. 3. t cf is a calculated value and is not guaranteed. t cf can be found using the following equation: t cf = 1/f max (internal feedback) C t s . parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c, f = 1 mhz 5pf c out output capacitance v out = 2.0 v 8 pf parameter symbol parameter description -15 -25 unit min max min max t pd input or feedback to combinatorial output 15 25 ns t s setup time from input or feedback to clock 12 15 ns t h hold time 0 0 ns t co clock to output 10 12 ns t wl clock width low 8 12 ns t wh high 8 12 ns f max maximum frequency (note 2) external feedback 1/(t s +t co ) 45.5 37 mhz internal feedback (f cnt ) 1/(t s +t cf ) (note 3) 50 40 mhz no feedback 1/(t wh +t wl ) 62.5 41.6 mhz t pzx oe to output enable 15 20 ns t pxz oe to output disable 15 20 ns t ea input to output enable using product term control 15 25 ns t er input to output disable using product term control 15 25 ns
318 palce20v8h-15/25 q-20/25 (ind) absolute maximum ratings storage t emperature . . . . . . . . . . . . . .-65 c to +150 c ambient t emperature with power applied . . . . . . . . . . . . . .-55 c to +125 c supply voltage with respect to gr ound . . . . . . . . . . -0.5 v to +7.0 v dc input v oltage . . . . . . . . . . . -0.5 v to v cc + 0.5 v dc output or i/o pin v oltage . . . . . . . . . . . . . . . . . -0.5 v to v cc + 0.5 v static discharge v oltage . . . . . . . . . . . . . . . . . 2001 v latchup current (t a = -40 c to +85 c) . . . . . . 100 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. programming conditions may differ. operating ranges industrial (i) devices ambient t emperature (t a ) operating in free air . . . . . . . . . . . . . . . . . . . . . . -40 c to +85 c supply voltage (v cc ) with respect to gr ound . . . . . . . . . . . +4.5 v to +5.5 v operating ranges de?ne those limits between which the functionality of the device is guaranteed. dc characteristics over industrial operating ranges notes: 1. these are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. parameter symbol parameter description test description min max unit v oh output high voltage i oh = -3.2 ma, v in = v ih or v il , v cc = min 2.4 v v ol output low voltage i ol = 24 ma, v in = v ih or v il , v cc = min 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs (note 1) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (note 1) 0.8 v i ih input high leakage current v in = 5.5 v, v cc = max (note 2) 10 a i il input low leakage current v in = 0 v, v cc = max (note 2) C100 a i ozh off-state output leakage current high v out = 5.5 v, v cc = max , v in = v ih or v il (note 2) 10 a i ozl off-state output leakage current low v out = 0 v, v cc = max , v in = v ih or v il (note 2) C100 a i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C150 ma i cc supply current outputs open (i out = 0 ma), v cc = max, f = 15 mhz h 130 ma q65
palce20v8h-15/25 q-20/25 (ind) 319 pal devices capacitance 1 note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modi?ed whe re capacitance may be affected. switching characteristics over industrial operating ranges 1 notes: 1. see switching test circuit for test conditions. 2. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modi?ed wh ere frequency may be affected. 3. t cf is a calculated value and is not guaranteed. t cf can be found using the following equation: t cf = 1/f max (internal feedback) C t s . parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c, f = 1 mhz 5pf c out output capacitance v out = 2.0 v 8 pf parameter symbol parameter description -15 -20 -25 unit min max min max min max t pd input or feedback to combinatorial output 15 20 25 ns t s setup time from input or feedback to clock 12 13 15 ns t h hold time 0 0 0 ns t co clock to output 10 11 12 ns t wl clock width low 8 10 12 ns t wh high 8 10 12 ns f max maximum frequency (note 2) external feedback 1/(t s +t co ) 45.5 41.6 37 mhz internal feedback (f cnt ) 1/(t s +t cf ) (note 3) 50 45.4 40 mhz no feedback 1/(t wh +t wl ) 62.5 50.0 41.6 mhz t pzx oe to output enable 15 18 20 ns t pxz oe to output disable 15 18 20 ns t ea input to output enable using product term control 15 18 25 ns t er input to output disable using product term control 15 18 25 ns
320 palce20v8 family switching waveforms notes: 1. v t = 1.5 v 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 ns to 5 ns typical. t pd input or feedback combinatorial output v t v t a. combinatorial output 16491e-5 t wh clock c. clock width v t t wl 16491e-7 v t input or feedback registered output b. registered output t s t co v t t h v t clock 16491e-6 v t v t input output d. input to output disable/enable t er t ea v oh C 0.5v v ol + 0.5v 16491e-8 v t v t oe output e. oe to output disable/enable t pzx t pxz v oh C 0.5v v ol + 0.5v 16491e-9
palce20v8 family 321 pal devices key to switching waveforms switching test circuit speci?cation s 1 c l commercial measured output value r 1 r 2 t pd , t co closed 50 pf 200 w 390 w 1.5 v t pzx , t ea z ? h: open 1.5 v z ? l: closed t pxz , t er h ? z: open 5 pf h-5: 200 w h ? z: v oh C 0.5 v l ? z: closed l ? z: v ol + 0.5 v must be steady may change from h to l may change from l to h does not apply dont care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs ks000010-pal c l output r 1 r 2 s 1 5 v 16491e-10
322 palce20v8 family typical i cc characteristics v cc = 5 v, t a = 25c i cc vs. frequency the selected typical pattern utilized 50% of the device resources. half of the macrocells were programmed as registered, and the other half were programmed as combinatorial. half of the available product terms were used for each macrocell. on any vector, h alf of the outputs were switching. by utilizing 50% of the device, a midpoint is de?ned for i cc . from this midpoint, a designer may scale the i cc graphs up or down to estimate the i cc requirements for a particular design. 150 125 100 75 50 25 0 01020304050 frequency (mhz) i cc (ma) 20v8h-5 20v8h-7 20v8h-10 20v8h-15/25 20v8q-10 20v8q-15/25 16491e-11
palce20v8 family 323 pal devices endurance characteristics the p alce20v8 is manufactured using v antis? advanced electrically-erasable (ee) cmos pr ocess. this technology uses an ee cell to replace the fuse link used in bipolar parts. as a result, the device can be erased and repr ogrammed?a feature which allows 100% testing at the factory. robustness features the palce20v8x-x/5 have some unique features that make them extremely robust, especially when operating in high-speed design envir onments. pull-up resistors on inputs and i/o pins cause unconnected pins to default to a known state. input clamping circuitry limits negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing. a special noise tlter makes the programming circuitry completely insensitive to any positive overshoot that has a pulse width of less than about 100 ns for the /5 versions. symbol parameter test conditions value unit t dr min pattern data retention time max storage temperature 10 years max operating temperature 20 years n max reprogramming cycles normal programming conditions 100 cycles
324 palce20v8 family input/output equivalent schematics for palce20v8h-7 and palce20v8h-5 typical input typical output feedback input esd protection and clamping v cc v cc programming voltage detection positive overshoot filter programming circuitry provides esd protection and clamping programming pins only preload circuitry device rev letter palce20v8h-7 a palce20v8h-5 a 16491e-12 v cc > 50 k w v cc > 50 k w
palce20v8 family 325 pal devices input/output equivalent schematics for /4 versions input i/o preload circuitry esd protection feedback input v cc v cc 0.5 k w 100 k w v cc v cc 100 k w 0.5 k w device rev letter palce20v8h-10 m palce20v8h-15 l, m palce20v8h-15 m palce20v8h--25 m palce20v8h-25 m 16491e-13 topside marking: vantis cmos plds are marked on top of the package in the following manner: palcexxx datecode (3 numbers) lot id (4 characters)CC(rev letter) the lot id and rev letter are separated by two spaces.
326 palce20v8 family power-up reset the palce20v8 has been designed with the capability to r eset during system power-up. following power-up, all ? ip-? ops will be r eset to low. the output state will be high independent of the logic polarity. this feature provides extra ?exibility to the designer and is especially valuable in simplifying state machine initialization. a timing diagram and parameter table are shown below. due to the synchronous operation of the power-up r eset and the wide range of ways v cc can rise to its steady state, two conditions are required to ensure a valid power -up reset. these conditions are: u the v cc rise must be monotonic. u following reset, the clock input must not be driven from low to high until all applicable input and feedback setup times are met. parameter symbol parameter descriptions min max unit t pr power-up reset time 1000 ns t s input or feedback setup time see switching characteristics t wl clock width low t pr t wl t s 4 v v cc power registered output clock 16491e-15 figure 2. power-up reset waveform
palce20v8 family 327 pal devices typical thermal characteristics measured at 25 c ambient. these parameters are not tested. plastic q jc considerations the data listed for plastic q jc are for reference only and are not recommended for use in calculating junction temperatures. the heat-?ow paths in plastic-encapsulated devices are complex, making the q jc measurement relative to a speci?c location on the pack- age surface. tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. furthermore, q jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant tem- perature. therefore, the measurements can only be used in a similar environment. parameter symbol parameter description typ unit pdid plcc q jc thermal impedance, junction to case 19 19 c/w q ja thermal impedance, junction to ambient 73 55 c/w q jma thermal impedance, junction to ambient with air ?ow 200 lfpm air 61 45 c/w 400 lfpm air 53 41 c/w 600 lfpm air 50 38 c/w 800 lfpm air 47 36 c/w
328 palce20v8 family connection diagrams top view pin designations 1 2 3 4 5 6 7 8 9 10 11 12 clk/i 0 i 1 i 2 i 3 i 4 i 5 i 6 i 7 i 8 i 9 i 10 gnd v cc i 13 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 i 12 oe /i 11 24 23 22 21 20 19 18 17 16 15 14 13 note: pin 1 is marked for orientation. skinnydip plcc oe /i 11 16491e-16 16491e-17 4 5 6 7 8 9 10 11 3 2 1 28 27 26 25 24 23 22 21 20 19 12 13 14 15 16 17 18 i 3 i 4 i 5 nc i 6 i 7 i 8 i/o 6 i/o 5 i/o 4 gnd/nc * i/o 3 i/o 2 i/o 1 i 9 i 10 gnd nc i 12 i/o 0 i 2 i 1 clk/i 0 nc v cc i 13 i/o 7 clk = clock gnd = ground i = input i/o = input/output nc = no connect oe = output enable v cc = supply voltage
palce20v8 family 329 pal devices ordering information commercial and industrial products vantis programmable logic products for commercial and industrial applications are available with several ordering options. the order number (valid combination) is formed by a combination of: valid combinations valid combinations list contgurations planned to be supported in volume for this device. consult the local vantis sales oftce t o contrm availability of specitc valid combinations and to check on newly released combinations. valid combinations palce20v8h-5 jc /5 palce20v8h-7 pc, jc palce20v8h-10 /4 palce20v8q-10 pc /5 palce20v8h-15 pc, jc, pi, ji /4 palce20v8q-15 pc, jc palce20v8q-20 pi, ji palce20v8h-25 pc, jc, pi, ji palce20v8q-25 number of flip-flops or outputs package type p = 24-pin 300 mil plastic skinny dip (pd3024) j = 28-pin plastic leaded chip carrier (pl 028) operating conditions c = commercial (0 c to +75 c) i = industrial (-40 c to +85 c) pa l c e 2 0 v 8 h - 5 j c speed -5 = 5 ns t pd -7 = 7.5 ns t pd -10 = 10 ns t pd -12 = 12 ns t pd -15 = 15 ns t pd -20 = 20 ns t pd -25 = 25 ns t pd family type pal = programmable array logic power h = half power (90e125 ma i cc ) q = quarter power (55 ma i cc ) technology ce = cmos electrically erasable number of array inputs output type v = versatile /5 programming designator blank = initial algorithm /4 = first revision /5 = second revision (same algorithm as /4)
330 palce20v8 family

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